Some memory devices, such as Flash devices, comprise multiple memory blocks. Various techniques for memory block management are known in the art. For example, U.S. Pat. No. 8,040,744, whose disclosure is incorporated herein by reference, describes techniques for management of spare blocks in a reprogrammable non-volatile memory system, such as a Flash EEPROM system. In one set of techniques, for a memory partitioned into two sections such as a binary section and a multi-state section, where blocks of one section are more prone to error, spare blocks can be transferred from the more error prone partition to the less error prone partition. In another set of techniques, blocks which fail in the more error prone partition are transferred to serve as spare blocks in the other partition.
As another example, U.S. Patent Application Publication 2010/0174847, whose disclosure is incorporated herein by reference, describes techniques in which a portion of a non-volatile memory is partitioned from a main multi-level memory array to operate as a cache. The cache memory is configured to store at less capacity per memory cell and finer granularity of write units compared to the main memory. The cache memory has a capacity dynamically increased by allocation of blocks from the main memory in response to a demand to increase the capacity. Preferably, a block with an endurance count higher than average is allocated. The logical addresses of data are partitioned into zones to limit the size of the indices for the cache.